We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs and delivers advanced System-on-Chip solutions across multiple emerging technologies. They provide high-performance custom solutions for cutting-edge applications. You'll collaborate with customers, frontend, and integration teams to ensure successful tape-outs, contributing across all phases of physical design. Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong communication skills, experience with multiple tape outs from inception, small company experience. Local candidates are preferred.
Key Responsibilities:
Pre-layout STA for feasibility and timing constraint validation
Chip/block-level floorplanning and pin assignment
Clock spec review and clock tree synthesis
Placement, routing, and timing optimization
Sign-off tasks: RC extraction, STA, IR-drop analysis, and physical verification
Customer meetings and technical presentations
Qualifications
BSEE with 5+ years experience; MSEE preferred
Strong experience in ASIC physical design and SoC development (28nm/16nm)
Proficient in ICC2/Innovus, scripting (Perl/Tcl/Python)
Knowledge of frontend design and hierarchical layouts
Familiar with power/IR-drop tools (PrimePower/Redhawk) and STA (PrimeTime)
Skilled in PV tools and debugging PV errors
Excellent communication and problem-solving skills
Why is This a Great Opportunity
Leading custom ASIC and SoC development company with a pipeline of new technology projects for top companies. Employees are real contributors, often working independently or as part of a small team. Will work of full project lifecycle from inception to tapeout.
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