Job Description

Overview:

Job Title: Senior Physical Design Engineer

Location: San Jose ,CA - Onsite

Experience level: 8-10 years

Candidate Roles and Responsibilities

•Perform RTL to GDSII tasks such Synthesis, PnR, CTS, Statis Timing Analysis, Physical verification and ensuring clean sign off. • Develop and maintain the tool flow to support the project • Work with Team to enhance PD methodology • LEC, CDC Basic Qualifications & Skills • Experience in advanced node processes 07nm and 05nm • Experience with industry standard tools, preference for Cadence flow • Understanding of RTL to GDSII flow • Understanding of timing constraints and static timing analysis (STA) • Experience with Synthesis, CDC (Clock Domain Crossing Checks), LEC (Logic Equivalence Checks), automation through scripting such as Perl, Python, Tcl & Mak Skills which we should not look for: Analog physical design, Any special or skills related notes: motivated technical person who wants to grow experience building large ASIC and exposure to work with multisite team. This job involves working from customer site. Any special or skills related notes: motivated technical person who wants to grow experience building large ASIC and exposure to work with multi-site team. This job involves working from customer site. Education: BS/MS in Electrical/Computer Engineering

Skills:

RTL,GDSII,Synthesis,CDC,LEC

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