Job Description

Physical Design Engineer-

Location: San Jose CA- 5 Days onsite

What will you do :

• Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure
• Setup and Synthesizing RTL
• Timing closure through various methods and strategies; preferable in-depth experience in

top-level STA

• EM/IR Analysis,
• Place and Route
• Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew

balancing techniques

• Floor-planning and Layout; preferable in-depth experience in top-level floorplanning
• Flow and Methodology Development
• Collaborating with IC Design RTL Engineers

What you will Bring:

• TCL/PERL Scripting
• Proficiency in related EDA Tools
• Full physical design cycle experience: RTL to Tape-out
• Excellent verbal and written communication skills

Education and Experience Requirements:

• Minimum: Bachelor’s degree required in Electrical Engineering or Electronics

Benefits:

• Bonus based on performance
• Paid time off
• Training & development

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